HDL

Note

Commands like: ngspice, verilator, gtkwave, ghdl must be run in a normal terminal. Other commands in the tutorial require OpenLane environment to be running in the terminal.

Preparing an own ASIC requires a prototype circuit described in one of the Hardware Description Language(HDL). In this chapter you will prepare a design of 4-bit counter and a testbench for simulations. Before starting simulations install Verilator.

sudo apt install verilator -y

VHDL

If the project is written in VHDL, it has to be converted to Verilog. First install GHDL.

sudo apt install ghdl -y

Then convert the project.

ghdl -a counter.vhd
ghdl synth --out=verilog counter > counter.v

Design

Describe a counter presented below using submodules in a RTL architecture. Use a below template in Verilog language, it will make simulations easier. Create a file named counter.v, copy a below text and write a code for all modules.

module jk_ff ( input j,
               input k,
               input clk,
               output reg q);

endmodule

module and_2( input a,
              input b,
              output y); 

endmodule

module counter( input clk,
                output [3:0] q, 
	        output p);

endmodule

Quartus

Simulation

Create file named tb.v in the directory where the counter.v file is, then copy the text below to the tb.v file.

module tb_counter;

reg clk;

wire [3:0]q;
wire p;

counter u0 ( .clk(clk),
	 .q(q),
         .p(p));

initial begin
$dumpfile("test.vcd");
$dumpvars;
	clk = 1;
	#320 $finish;
end

always #10 clk=~clk;

always #20 $display("%d %d",p,q);

endmodule

To run a simulation use verilator. The line below will compile testbench to binary version and run the simulation.

verilator --trace --binary -j 0 tb.v
./obj_dir/Vtb

The simulation will print the values from the counter for each clock cycle.

Install and run gtkwave to see the results in the time domain.

sudo apt install gtkwave -y
gtkwave test.vcd

GTKWAVE