We reduced the above problems to sets of linear equations which we solved by rather procedural methods. This approach can be inconvenient in some situations. For that reason closed-form expressions were proposed in [MG94] to solve the basic model of the chain architecture. It was also shown that in the linear arrays of identical processors with the originator located in the network interior, the whole load processing time is independent of the direction the originator sends the data first. The case of the originator located inside the chain was analyzed in [BD97,MG94], and the case of rings of PEs in [BD97]. In [BR92,Ro93] a concept of the equivalent processor was proposed, by which a single-processor equivalent of the original multiprocessor system was understood. The ultimate performance limits were calculated. In [GM94] closed-form formulae expressing the limit of the performance enhancement obtained by using additional processors are presented. [BGM95b] examines a chain network in which PEs are equipped with 1-port network processors. This means that a PE can communicate only over one link at a time. By the use of the intermediate PEs' network processors the originator sends the shares of data directly to a particular PE. Thus, any PE can start computing right after receiving its data, without waiting for the load being forwarded to the following PEs. In the previous discussion we assumed that the originator sent the data to its neighbors in one chunk. This may result in long communication delays and idle period on PEs before computing can be started. In [D97] a different data distribution method based on pipelining and circuit-switched routing was proposed, i.e. rather than in one big chunk the data are sent to the PEs in many smaller ones.