-- Program sumuje dwie liczby z zakresu od 0 do 9 i wyswietla wynik 
-- na 7-segmentowych wyswietlaczach. Przekroczenie zakresu sygnalizowane
-- jest litera 'E' (Error). Na wejsciu uzytkownik podaje za pomoca
-- przelacznikow sw(0)-sw(3) oraz sw(4)-sw(7) dwie liczby 4-bitowe.
-- Stan przelacznikow wyswietlany jest na diodach czerwonych oraz na
-- wyswietlaczach hex6 i hex4. Suma w postaci liczby w systemie
-- dziesietnym wyswietlana jest na wyswietlaczach hex0 i hex1.

library IEEE;                  -- dolaczenie standardowej biblioteki IEEE
use IEEE.STD_LOGIC_1164.all; 

entity an_ex is                -- glowny element projektu
   port ( 
      sw: in std_logic_vector(0 to 7);
      ledr: out std_logic_vector(0 to 7);
      hex0: out std_logic_vector(0 to 6);
      hex1: out std_logic_vector(0 to 6);
      hex2: out std_logic_vector(0 to 6);
      hex3: out std_logic_vector(0 to 6);
      hex4: out std_logic_vector(0 to 6);
      hex5: out std_logic_vector(0 to 6);
      hex6: out std_logic_vector(0 to 6);
      hex7: out std_logic_vector(0 to 6)
   );
end an_ex;

architecture ar_ex of an_ex is

   signal s: std_logic_vector(0 to 7);

   component digit
      port( 
         we: in std_logic_vector(0 to 3);
         wy: out std_logic_vector(0 to 6)
      );
   end component;

   component sum
      port(
         n1: in std_logic_vector(0 to 3);
         n2: in std_logic_vector(0 to 3);
         wy: out std_logic_vector(0 to 7)
      );
   end component;

begin
   hex2 <= "1111111";
   hex3 <= "1111111";
   hex5 <= "1111111";
   hex7 <= "1111111";
   ledr <= sw;
   i1: digit port map (sw(4 to 7), hex6(0 to 6));
   i2: digit port map (sw(0 to 3), hex4(0 to 6));
   i3: sum port map (sw(0 to 3), sw(4 to 7), s(0 to 7));
   i4: digit port map (s(4 to 7), hex1(0 to 6));
   i5: digit port map (s(0 to 3), hex0(0 to 6));
end ar_ex;

library IEEE;                  
use IEEE.STD_LOGIC_1164.all; 
entity digit is                -- translacja wektora binarnego na cyfre dziesietna
   port ( 
      we: in std_logic_vector(0 to 3);
      wy: out std_logic_vector(0 to 6)
   );
end digit;

architecture ar_di of digit is
begin
   process (we)
   begin
      if (not we(3) or (not we(2) and not we(1)))='1' then 
         wy(0) <= not (we(1) or we(3) or (we(0) and we(2)) or (not we(0) and not we(1) and not we(2)));
         wy(1) <= not (we(3) or not we(2) or (not we(0) and not we(1)) or (we(0) and we(1)));
         wy(2) <= we(1) and not we(0) and not we(2);
         wy(3) <= not (we(3) or (not we(0) and we(1)) or (not we(2) and we(1)) or 
            (we(0) and not we(1) and we(2)) or (not we(0) and not we(2)));
         wy(4) <= not ((not we(0) and not we(2)) or (not we(0) and we(1))); 
         wy(5) <= not (we(3) or (not we(0) and not we(1)) or (not we(1) and we(2)) or (not we(0) and we(2)));
         wy(6) <= not (we(3) or (not we(1) and we(2)) or (not we(0) and we(1)) or (we(1) and not we(2)));
      else
         wy <= "0110000";
      end if;
   end process;
end ar_di;

library IEEE;                  
use IEEE.STD_LOGIC_1164.all; 
entity sum is                  -- sumowanie dwoch liczb binarnych
   port (
      n1: in std_logic_vector(0 to 3);
      n2: in std_logic_vector(0 to 3);
      wy: out std_logic_vector(0 to 7)
   );
end sum;

architecture ar_su of sum is

procedure transl(variable b: inout std_logic_vector(0 to 7)) is            
begin                          -- zamiana liczby szesnastkowej <19 na dziesietna
   if (b(4) or (b(3) and (b(2) or b(1))))='1' then
      if b(4)='1' then
         b(4) := '0';
         b(2) := '1';
         if b(1)='0' then
            b(1) := '1';
         else
            b(1 to 2) := "00";
            b(3) := '1';
         end if;
      else 
         if b(1)='0' then
            b(2 to 3) := "00";
            b(1) := '1';
         else 
            b(3) := '0';
            b(1) := '0';
         end if;
      end if;
      b(4) := '1';
   end if;
end transl;

begin
   process (n1,n2)
   variable a: std_logic_vector(0 to 7);
   begin
      if ((not n1(3) or (not n1(2) and not n1(1))) and (not n2(3) or (not n2(2) and not n2(1))))='1' then 
         a := "00000000";
         for i in 0 to 3 loop
            if n1(i)='1' then 
               if a(i)='0' then
	          a(i) := '1';
               else
	          a(i) := '0';
                  a(i+1) := '1';
               end if;
            end if;
            if n2(i)='1' then 
               if a(i)='0' then
	          a(i) := '1';
               else
	          a(i) := '0';
                  a(i+1) := '1';
               end if;
            end if;
         end loop;
         transl(a);
         wy <= a;
      else
         wy <= "11111111";
      end if;
   end process;
end ar_su;